The processing of a request by one processor of a computing environment may affect one or more other processors of the environment. For example, in a Symmetric Multiprocessor System (SMP) based on the z/Architecture of International Business Machines Corporation, Armonk, N.Y., a broadcast purge operation, such as an Invalidate Page Table Entry (IPTE) instruction, requires entries of one or more buffers (e.g., Translation Lookaside Buffers (TLBs)) to be removed from the buffers in all processors of the environment. Furthermore, the architecture requires the buffers to be purged atomically, such that no processor can observe a new TLB entry, while some other processor observes an old entry. Many other computer architectures also provide a similar mechanism.
One common implementation for the broadcast purge operation includes the following: 1) all processors are quiesced (i.e., most normal processing operations are suspended, including accessing the TLB); 2) TLBs on all processors are purged of the appropriate entries; 3) the common resource is changed (e.g., a page table entry in storage for IPTE); and 4) finally, the quiesce is released and the processors continue their normal activities. Obviously, this implementation could have a major performance impact, especially for large SMP configurations, since all processors must be quiesced for the duration of the operation. In particular, it is common that one processor is executing some long running instruction that is not interruptible, so it cannot reach the quiesce state for some time. Thus, all other processors are required to wait for this last processor to reach the quiesce state before the steps described above can be completed.
Some strides have been made in the above processing to enhance performance. For example, in U.S. Pat. No. 6,119,219, entitled “System Serialization With Early Release Of Individual Processor,” Webb et al., Sep. 12, 2000, and U.S. Pat. No. 6,079,013, entitled “Multiprocessor Serialization With Early Release of Processors,” Webb et al., Jun. 20, 2000, each of which is hereby incorporated herein by reference in its entirety, a technique is described in which processors are potentially quiesced for a shorter period of time. For example, when a processor receives a request, it immediately quiesces and then purges the appropriate entries in its own TLB. After the purge is complete, this processor is allowed to continue processing subject to various restrictions. One of these restrictions includes that if the processor misses in its TLB, it is not permitted to perform address translation, but instead must stall until the quiesce is released. Only after the quiesce is released are all restrictions removed from the processors and processing can continue.
Thus, although attempts have been made to reduce the amount of time processors are stalled, enhancements are still needed. For example, a need exists for a capability that enables processing restrictions to be blocked, such that processing can continue, despite the restrictions.